Electric double layer capacitor (EDLC) impedance measurement is the fundamental electrochemical technique used to determine the equivalent series resistance (ESR), capacitance, and frequency response of supercapacitors. Using electrochemical impedance spectroscopy (EIS) in accordance with international standards such as IEC 62391, accredited third-party laboratories and manufacturers can accurately assess device quality, power capability, and long-term reliability. This article explains the measurement principles, sample types, test items, standard test methods, and typical applications of EDLC impedance testing.
Technical Overview
An electric double layer capacitor (EDLC), commonly known as a supercapacitor or ultracapacitor, stores energy electrostatically by separating charges at the interface between high-surface-area activated carbon electrodes and an electrolyte. Unlike batteries, no faradaic redox reaction is involved in the ideal case, which gives EDLCs extremely high cycle life, rapid charge and discharge capability, and power densities far exceeding those of secondary batteries. However, the practical performance of an EDLC is governed by internal losses and distributed charge storage behavior that cannot be fully captured by a simple capacitance value.
Impedance measurement addresses this limitation by characterizing the device as a complex, frequency-dependent impedance Z(ω), where ω is the angular frequency of an applied sinusoidal perturbation. The measured impedance consists of a real component Z' (resistive) and an imaginary component Z'' (reactive), which are conventionally presented as a Nyquist plot, a Bode magnitude plot, and a phase angle plot. From these spectra, engineers extract the equivalent series resistance, the effective capacitance at defined frequencies, the characteristic time constant, and diagnostic signatures of electrode porosity, electrolyte degradation, and contact defects.
Because EDLC electrodes are porous, their impedance response exhibits a distinctive shape: a high-frequency intercept corresponding to bulk electrolyte and lead resistance, a 45-degree sloped region at intermediate frequencies arising from distributed resistance and capacitance inside the pores, and a near-vertical capacitive line at low frequencies. Quantitative interpretation of these features is the essence of professional EDLC impedance determination and is essential for product qualification, incoming inspection, and reliability engineering.
Testing Samples
Commercial EDLC Single Cells
Mass-produced cylindrical, prismatic, and laminated pouch cells with capacitances typically ranging from 1 F to 3000 F are the most common test specimens. These devices are tested as received, after voltage conditioning at rated voltage, or after defined environmental exposure. Terminal surfaces are cleaned and connected using four-terminal (Kelvin) fixtures to eliminate contact and cable resistance from the measurement.
EDLC Modules and Stacks
Series-connected modules used in rail transit, hybrid vehicles, and grid support are tested to evaluate the uniformity of individual cells, the impedance contribution of busbars and interconnects, and the overall ESR relevant to power electronics design. Module-level testing often requires higher current excitation and careful shielding to suppress electromagnetic interference.
Laboratory Coin Cells and Three-Electrode Cells
In research and development, symmetric coin cells assembled from candidate electrode materials, or three-electrode half-cells with a reference electrode, are measured to separate anode and cathode contributions and to benchmark new carbons, electrolytes, and binders. Half-cell impedance data are frequently normalized to electrode mass or geometric area for material comparison.
Aged and Cycled Specimens
Cells extracted from endurance testing, such as high-temperature voltage holding, load cycling, or humidity exposure, are measured to track ESR growth and capacitance fade. Impedance spectra of aged specimens reveal whether degradation originates from electrolyte dry-out, increased contact resistance, or pore blockage, providing actionable feedback for design improvement.
Testing Items
A comprehensive EDLC impedance determination typically includes the following measurable quantities, each of which is reported as a function of temperature, DC bias, and state of charge where applicable:
- Equivalent series resistance (ESR) at 1 kHz and other specified frequencies, per IEC 62391-1
- DC ESR derived from the instantaneous voltage drop during constant current discharge, for comparison with AC ESR
- Effective capacitance calculated from the low-frequency imaginary impedance, C = -1/(ωZ'')
- Characteristic time constant τ, defined as ESR multiplied by C, or as 1/(2πf₀) at the -45 degree phase point
- Impedance magnitude and phase angle across the full frequency range, typically 1 mHz to 100 kHz
- Distributed resistance and distributed capacitance of the porous electrode, extracted from the 45 degree region
- Parallel leakage resistance associated with self-discharge and faradaic side reactions
- High-frequency inductive contribution from terminals and current collectors
- Temperature dependence of ESR and capacitance, typically from -40 °C to +70 °C
- DC bias dependence of capacitance and resistance at 0 V, 50 percent, and 100 percent of rated voltage
Testing Methods
Potentiostatic Electrochemical Impedance Spectroscopy
In the potentiostatic configuration, a small sinusoidal voltage, typically 5 to 10 mV in amplitude to preserve linearity, is superimposed on a chosen DC bias and applied across the cell terminals. The frequency is swept logarithmically from high frequency, typically 100 kHz, down to the low-frequency limit, commonly 1 mHz or 10 mHz. The ratio of the measured current response to the voltage perturbation yields the complex impedance at each frequency. The small amplitude ensures that the capacitor operates in its linear region, which is a prerequisite for valid impedance data.
Galvanostatic EIS
For very low-ESR, high-capacitance devices, potentiostatic excitation may produce unmeasurably small currents. In galvanostatic EIS, a small sinusoidal current, usually limited to a few percent of the rated current, is applied and the resulting voltage response is analyzed. This configuration provides superior signal-to-noise ratio for large cells and modules and is widely used for production line ESR screening at 1 kHz.
Equivalent Circuit Fitting and Data Validation
The measured spectrum is fitted to an equivalent circuit appropriate to porous carbon electrodes. A minimal model comprises a series resistance, a small series inductance, and a capacitance, while refined models use a transmission line structure or constant phase elements to represent the distributed pore impedance. Validity of the data is checked through repeatability runs and, where required, Kramers-Kronig consistency tests that verify the linearity, stability, and causality assumptions of the measurement. Capacitance is reported at a defined low frequency where the phase angle approaches -90 degrees, and ESR is reported at 1 kHz unless otherwise specified.
Applicable Standards
Professional impedance determination is performed in accordance with recognized international and national standards, including the IEC 62391 series for fixed electric double layer capacitors, IEC 61881-3 for capacitors in railway rolling stock power electronics, GB/T 34870.1 for supercapacitor general specifications, and UL 810A covering electrochemical capacitors. These standards define the measurement circuit, excitation amplitude, frequency points, temperature conditions, and calculation formulas so that results from different accredited third-party laboratories are directly comparable.
Applications
EDLC impedance data directly support design decisions and quality assurance across a broad range of industries:
- Automotive start-stop and mild hybrid systems, where ESR determines cranking assist capability and thermal losses
- Hybrid and electric buses using regenerative braking energy recovery, where time constant governs charge acceptance
- Rail transit wayside energy storage and onboard pantograph voltage stabilization
- Grid frequency regulation and renewable power smoothing, where module impedance affects converter sizing
- Wind turbine pitch control backup power and actuator emergency retractions
- Uninterruptible power supplies, memory backup, and smart meter hold-up circuits
- Medical and industrial pulse power devices such as defibrillators and actuator drivers
- Manufacturing quality control, incoming component inspection, and failure analysis of returned field samples
FAQ
Why is ESR commonly specified at 1 kHz?
At approximately 1 kHz, the impedance of a typical EDLC is almost purely resistive because the capacitive reactance of the accessible pore structure has collapsed while inductive effects remain negligible. IEC 62391 therefore designates 1 kHz as the reference frequency for AC ESR, enabling consistent comparison between products and laboratories.
What is the difference between AC ESR and DC ESR?
AC ESR measured at 1 kHz reflects only the rapidly accessible resistive contributions, whereas DC ESR derived from the voltage step in a constant current discharge also includes the distributed resistance of deep pores that only charge at low frequency. DC ESR is consequently higher, and both values are needed to fully characterize power losses during fast and slow discharge regimes.
How is capacitance obtained from an impedance spectrum?
In the low-frequency region where the Nyquist plot approaches a vertical line, the capacitance is calculated as C = -1/(ωZ''), where ω is the angular frequency and Z'' is the imaginary impedance. Reporting the measurement frequency alongside the capacitance value is essential because EDLC capacitance decreases with increasing frequency.
What causes the 45 degree region in the Nyquist plot?
The 45 degree slope is the signature of a porous electrode, described by transmission line models in which electrolyte resistance and interfacial capacitance are distributed along the pore depth. Its length indicates how much of the internal surface is electrochemically accessible at a given frequency, and its growth with aging signals pore blockage or electrolyte depletion.
How long does a full impedance measurement take?
Test duration is dominated by the lowest frequency, since at least two full cycles of the sinusoid are required per point. A sweep down to 1 mHz alone takes roughly 30 to 40 minutes, while a practical 10 mHz to 100 kHz spectrum is typically completed in 10 to 20 minutes, excluding temperature stabilization time.
Can impedance testing damage the sample?
No. When performed correctly with amplitudes of a few millivolts or a small fraction of rated current, the perturbation is non-destructive and the cell voltage never leaves its safe operating window. Impedance spectroscopy is therefore classified as a non-destructive test and the same specimen can be retested throughout an aging study.